1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and in particular to a semiconductor integrated circuit with less interconnect delay time so that high speed operation is realized when the integration level is increased.
2. Description of the Related Art
In the fabrication of very large scale integrated circuits (VLSIs), multilayer wirings are required to be miniaturized along with the scaling of the circuits in response to the request for a higher integration level of the circuits. However, as the wirings are miniaturized, the interconnect delay increases. The increase of the interconnect delay makes it difficult to maintain the circuit performance according to the trend of the scaling.
The interconnect delay increases when the length of a wiring between the input and output thereof increases. FIG. 14 shows a conventional bus wiring arrangement (including n bus wirings in FIG. 14). Referring to FIG. 14, bus input signals VIN0(i) (i=1 to n) pass through respective bus wirings W0(i) and are output as bus output signals VOUT0(i). Drivers D0(i) drive the respective bus wirings W0(i).
FIG. 15 is a structural sectional view of the bus wirings W0(i) taken along line A--A of FIG. 14. Referring to FIG. 15, the wiring layer of the bus wirings W0(i) is formed over a wiring layer 151 having an interlayer insulating film 152 therebetween. The reference codes L0, S0, T0, and H0 denote the width of the bus wirings W0(i), the spacing between the bus wirings W0(i), the thickness of the bus wirings W0(i), and the thickness of the interlayer insulating film 152 between the bus wirings W0(i) and the wiring layer 151, respectively.
In order to miniaturize the wirings, all of the n bus wirings, for example, must be scaled down, i.e., narrowed. This increases the wiring resistance and thereby the interconnect delay to such a degree that the interconnect delay cannot be neglected.
Hereinbelow, the degree to which the miniaturization of the wirings actually increases the interconnect delay is roughly estimated. In the following estimation, assume that the scaling factor is K, i.e., the design rule is reduced to 1/K every generation.
As a semiconductor integrated circuit is miniaturized, the chip area of the LSI is reduced. In recent years, however, some elements with different functions which were used to be formed on separate LSI chips tend to be integrated onto one LSI. This is because, in an inter-chip signal transmission (where a signal is output outside a chip and received on another chip), signal delay is larger by one or two orders of magnitude than an inner-chip signal transmission. Accordingly, the chip area of one LSI tends to increase. In this estimation, therefore, it is assumed that the chip area is fixed, i.e., the wiring length is fixed.
When the width, the spacing, and the thickness of the wirings and the thickness of the interlayer film are scaled down to 1/K, the wiring capacitance is maintained, but the wiring resistance is increased by a factor K.sup.2, thereby increasing the so-called wiring RC delay by the factor K.sup.2. While the gate delay is reduced to 1/K with the scaling, the wiring RC delay is relatively increased at a rate of K.sup.3 times when the delay of the entire wirings scaled down to 1/K is used as the reference.
The following methods have been proposed to reduce the increased interconnect delay due to wiring miniaturization.
(1) The wiring material is changed from aluminum (Al) to copper (Cu) to reduce the wiring resistance, and the material of the interlayer film is changed from SiO.sub.2 to SiOF with a low dielectric constant to reduce the wiring capacitance. This method is described, for example, in IEEE, 1993, IEDM Technical Digest, pp. 261-264.
(2) A hierarchical wiring structure is adopted, where the width and the thickness are scaled down for the wirings which are shortened during the miniaturization, while they are increased for the wirings which are not shortened, but rather lengthened during the miniaturization. This method is described, for example, in IEEE, 1994, IEDM Technical Digest, pp. 273-276.
The above methods, however, are not sufficient for MOS type integrated circuits which are fabricated based on the design rule of deep submicrons for the following reasons.
As for method (1) of changing the wiring material and the material of the interlayer film, the reduction of the wiring resistance obtained by changing the wiring material from Al to Cu is only about 37%, and the reduction of the wiring capacitance obtained by using a material with a low dielectric constant is only about 25%. These reductions are too small to counteract the increased interconnect delay due to the scaling.
As for method (2) of adopting a hierarchical wiring structure, the size of the miniaturized wirings and the size of the non-miniaturized wirings become unbalanced, thereby increasing the area of the non-miniaturized wirings. As a result, high integration is not possible.